약반전 증폭기를 이용한 4차 ΣΔ변조기 설계

초록

This paper describes a low power 4th order ΣΔ modulator for an implantable chip to acquire bio signals such as EEG(Electroencephalogram) or ECG(Electrocardiography) and EMG(Electromyography). In order to reduce a power consumption of the proposed modulator, an OP-Amp operating in a subthreshold region is employed with a time-interleaving technique. The proposed time-interleaving method allows the proposed modulator to utilize two op-amps operating in a subthreshold region two times and to behave as 4th order delta-sigma modulator which usually requires four op-amps. The chip is fabricated in a 0.18um CMOS n-well 1 poly 6 metal process. The core chip area occupies 950um x 800um, and the chip consumes 360uW with a power supply voltage of 1.8V. Simulation results show SNDR of 85.7dB and ENOB(Effective Number Of Bit) of 13.9bit, at input signal bandwidth of 1kHz and clock frequency of 512kHz.