Micro- and Nano-Scaled Gap Pattering Techniques for Thin-Film Transistor and Logic Gate Applications

초록

In the past few years, the two-dimensional (2D) van der Waals (vdW) materials have been extensively studied as a promising future electronic and optoelectronic materials due to their unique and interesting physical properties. There are several ways to fabricate the thin-film transistor (TFT) based application devices, such as logic gate circuits, memory devices, sensor system and etc., using conventional photolithography and E-beam lithography processes. In this work, we demonstrated very simple device fabricating methods to realize from micro- to nano-scaled electronic devices by employing a microfiber and a nanowire as shadow masks in deposition process. As a first approach, we can successfully obtain micro-scaled TFTs and CMOS logic inverter without any chemical usage and wet processes by using the shadow mask consisting of the PDMS mold and melt-blown microfibers [1]. A second method is a nanowire based nanogap pattering technique, which can be used as device fabrication methods for the nano-scaled S/D electrodes or a pair of separated gate electrodes to demonstrate functionalized TFTs and its applications. It allows to form sub 100 nm separated electrodes through conventional photolithography and lift-off processes, and the gap distance is defined by a diameter of nanowire. Base on this nano-pattering process, the PdSe2 based reconfigurable pn junction diode and advanced single-inversion AND (SAND) logic gate are implemented [2,3]. For another example, the MoS2 based AND-TFT and OR-TFT switching devices, which have longitudinal and transverse split gate electrodes against the channel direction, are successfully implemented for a NAND and a NOR logic circuit applications.