Atomistic Process and Simulation in the Regime of sub-50nm Gate Length

초록

In this paper, we report an atomistic simulation approach for sub-50nm gate length FETs. The proposed atomistic approach consists of the coupling the molecular dynamics (MD) simulations of the collision cascades for ion implantation process and Kinetic Monte Carlo (KMC) simulations for the subsequent diffusion process. The impurity profiles from the MD and KMC calculations were interfaced with the quantum-mechanical device simulations. The device performance of FinFET with 20nm physical gate length is discussed in this paper.