An Effectove Extraction of Distributed PLC Circuit Model for Multi-level Interconnects by Layout-Fracturing Algorithm

초록

In this paper, we propose a layout-fracturing algorithm for the estimation of signal delay at multi-level interconnects. The proposed algorithm divides layout into three types of segments, slsctrical node segments, resistive directly into a complex PLC circuits by PEEC model, and these segments define each simulation domain and the boundary condition for extracting the parasitics in the distributed PLC network. In order to extract a set of resistance, inductance and capacitance, we solve Maxwell's Equation together with continuity equation over dieldctrics and conbuctors mediurn using the finite slsment method(FEM)