Comparative PSR Analysis of a Domino-Like-Buffered LDO for Supply Noise Suppression

초록

This paper presents a comparative power supply rejection (PSR) analysis between conventional low-dropout regulator (LDO) [2] and domino-like-buffered (DLB) LDO [1] in a 28-nm CMOS process. The conventional LDO is based on a standard internal-pole-dominant structure. In contrast, the DLB LDO utilizes a dual-loop flipped voltage follower, segmented pass transistors, and a ripple-injected supply-ripple cancellation technique. To ensure a fair comparison, both structures were simulated under identical total power consumption and 200-pF total capacitance. Simulation results validate DLB LDO’s superiority, demonstrating a 10-dB improvement in PSR at 1 MHz. It also confirms stability with a 67-dB DC loop gain and 229-MHz UGF with 54° phase margin.