A Digital LDO with Single-VCO-Based Time Quantizer for Fast Load-Transient Response

초록

This paper presents a digital low-dropout regulator employing a single-VCO-based AC-coupled time quantizer and a three-level switched-capacitor (SC) gate driver for fast transient response and reduced output ripple. The proposed time quantizer dynamically increases the clock frequency in response to VOUT change, eliminating the need for dual voltage controlled oscillators (VCOs). Implemented in a 28?nm CMOS process, it achieves a 12.9?ns faster settling time and 28.2?mV lower voltage droop compared to prior work. Moreover, it exhibits the lowest quiescent current of 123.6 μA at a load current of 200 mA.