Interface Engineering of Chip Surfaces via Silane Treatments for Robust Underfill Adhesion

초록

In this study, a silane-assisted surface modification approach is developed to improve the interfacial reliability of underfill@solder bump assemblies in advanced semiconductor packaging. Conventional underfill processes frequently experience void formation and interfacial delamination at the solder bump and underfill interface, primarily due to inadequate wetting and thermally induced stress accumulation. However, effective interfacial engineering strategies for improving wetting at solder bump surfaces remain limited. To mitigate these issues, three silane coupling agents, (3-aminopropyl)triethoxysilane (APTES), (3-glycidyloxypropyl)trimethoxysilane (GPTMS), and phenyltriethoxysilane (PTES), were applied to solder bump surfaces via a solution-based immersion process. Comparative interfacial analysis revealed that GPTMS- and PTES-treated assemblies formed uniform and continuous underfill-solder interfaces with markedly reduced void formation. From the cross-section optical microscopy images, the interfacial coverage ratio was measured to be 99.2% for pristine assembly and increased to 99.9% for GPTMS- and PTES-treated assembly, confirming improved interfacial wetting. Thermal reliability evaluation conducted at 150 degrees C for up to 500 h demonstrated that glycidyl- and phenyl-based silanes effectively suppressed void growth and interfacial delamination, with PTES exhibiting the highest interfacial stability under prolonged thermal exposure. These results highlight the critical role of silane interfacial chemistry in governing underfill adhesion and long-term reliability in high-density semiconductor packaging.

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