회로 복잡도를 개선한 AOP기반의 GF(2m) 승산기

초록

This study focuses on the new hardware design of fast and low-complexity multiplier over GF(2m). The proposed multiplier based on the irreducible all one polynomial(AOP) of degree m, to reduced the system's complexity. It composed of Cyclic Shift, Partial Product, and Modular Summation Blocks. Also it consists of (m+1)2 2-input and gates and m(m+1) 2-input XOR gates. Out architecture is very regular, modular and therefore, well-suited for VLSI implementation.