An Optimal Design Methodology for Yield-Improved and Low-Power Pipelined ADC

초록

An energy-efficient, high-performance, and yield-improved analog to digital converter (ADC) design using a multi-objective evolutionary algorithm is demonstrated. The proposed ADC design algorithm incorporates several techniques to enable simultaneous improvement of yield and performance. With the same accuracy, the proposed approach can achieve a significant reduction of computational burden compared with the modified Monte-Carlo (MC)-based yield improvement methods integrating Latin-hypercube sampling or trimmed-sample MC. A prototype chip based on the proposed design is fabricated in a 0.13-mu m CMOS process at 150 MS/s. The results show the ADC achieves an SFDR of 65.48 dB and SNDR of 58.15 dB while dissipating 12 mW from a 1-V power supply. The results also yield a figure of merit of 121 fJ/conversion step.

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