Three-Dimensional Pipeline ADC Utilizing TSV/Design Optimization and Memristor Ratioed Logic

초록

High-performance, low-power-consumption, and high-accuracy analog-to-digital converters (ADCs) with a compact area are necessary for a wide range of current applications. This paper presents a pipeline ADC architecture with a novel 3-D clock distribution network utilizing through-silicon via-induced benefits. It also implements memristor ratioed logic as the basic elements of digital error correction subblock to further decrease the area, delay, and power consumption. In addition, an optimization technique using computational intelligence is applied to maximize the overall system performance. The proposed 3-D pipeline ADC is designed in a 65-nm CMOS technology and shows significant improvement regarding dynamic performance, energy efficiency, area, and clock accuracy compared with that of conventional 2-D ADC designs.

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