Design of 9-bit low power differential SAR ADC

초록

The block diagram of the proposed 9-bit low power SAR ADC is shown in Fig. 1. The proposed SAR ADC consists of differential 9bit C-DAC with split-capacitor, SAR Logic, latch comparator, reset generator, and output register. In Conventional C-DAC, binary weighted structure is used. The total capacity of the 9bit C-DAC is 512C in binary weighted structure. However designed C-DAC is reduced to 48C by using a split-capacitor. Using split-capacitor reduced capacity of the C-DAC about 90.6%. Operable minimum supply voltage of all circuits is 1V. Consequently, unit capacitor in the C-DAC is used 22fF that minimum capacity is provided by the process. Lower the power supply voltage, reducing the total amount of the capacitor, it was possible low power design.