Design of a low power 4th Order ΣΔ Modulator with the reused opamps

초록

This paper describes a low power 4th order ΣΔ modulator for an implantable chip to acquire bio signals such as EEG(Electroencephalogram) or DBS(Deep Brain Stimulation) and EMG. To reduce a power consumption of the proposed modulator, only two opamps are employed for the four integrators with the KT/C noise reduction circuit. A test chip was fabricated in a 0.18um CMOS n-well 1 poly 6 metal process. The chip core area occupies 900um x 800um, and its power is 900uW with a 1.8V supply voltage. Measurement results show 90dB of SNDR and 96dB of DR. We achieve 14.8bit at the input frequency and clock frequency of 1kHz and 256kHz, respectively. FOMs are 164dB(FOM1) and 12.7pJ/step(FOM2).