WLAN을 위한 5.2GHz_2.4GHz CMOS 2중대역 주파수 합성기의 설계

초록

This paper presents a Phase Locked Loop(PLL)-based frequency synthesizer(FS) which is designed in a standard 0.18 ㎛ CMOS 1P6M process for 5.2GHz/2.4GHz dual band wireless applications. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor Array (SCA) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The gain of VCO is 500MHz/V and the locking time is 5 ㎲ . The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 4.9GHz with SCA circuit on.