An FPGA Implementation of CNN-based Compression Artifact Reduction

초록

This paper proposes a convolutional neural network (CNN) based compression artifact reduction hardware. The proposed CNN architecture is applied to re-parameterization and INT8 quantization methods for efficient inference in edge devices. As a result of applying the optimization methods, the model size was reduced by x5.62, and the number of operations was reduced by x1.72. The proposed hardware achieves a frame rate of 33.33 FPS when implemented on a Xilinx ZCU104 SoC.

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