A New Dual-Engine Error Recovery Scheme for High-Reliability HBM

초록

Modern AI platforms increasingly depend on HBM-equipped accelerators, where uncorrectable memory errors can interrupt long-running workloads and reduce service availability. This paper proposes an S-ECC assisted decoding method for dual-engine detected-error (DE)+DE recovery in an HBM3-like two-engine OD-ECC structure. The method replaces CRC-16 S-ECC with RS(34,32) S-ECC and uses the additional syndromes to verify structured SWD fault-column candidates. It reuses the existing ECC storage budget for cross-tier verification. By reducing DE+DE recovery to a bounded candidate check, the proposed decoder corrects errors otherwise reported as uncorrectable. This bounded search improves recovery efficiency by avoiding arbitrary error-location search. Simulations show an 86.78% correction rate at p=1.0, while preserving the 18.75% HBM ECC data overhead and requiring no additional check bits. © 2026 IEEE.

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