An FPGA-based Lightweight Deblocking CNN for Edge Devices

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초록

The demand for multimedia data is rapidly increasing in many applications running on edge devices. The data compression method is essential for efficient communication in limited network bandwidth. However, the compressed data contains blocking artifacts that cause perceptual quality degradation and visual recognition problems. Recently, deep learning-based works have shown excellent progress in deblocking tasks. However, most previous works have used complex and deep network architectures that require high computational cost and large amounts of memory to improve performance. Therefore, deploying these networks as edge device applications is highly challenging work. In this paper, we propose an FPGA-based lightweight deblocking convolutional neural network (CNN) for edge devices. We present a lightweight CNN architecture to efficiently reduce blocking artifacts in the color domain. In addition, two optimization methods were introduced to further decrease the computation and memory requirement. Compared with CNNs proposed in other works, the number of MAC operations and the model size were reduced by approximately x145 and x2,300, respectively. Finally, the proposed deblocking CNN has been implemented on a ZCU104 FPGA board. As a result of measuring the frame rate, it achieved 30.73 FPS.

키워드

blocking artifactdeblockingconvolutional neural networkedge deviceFPGA
제목
An FPGA-based Lightweight Deblocking CNN for Edge Devices
저자
Kim, JaemyungKang, Jin-KuKim, Yongwoo
DOI
10.1109/ISCAS46773.2023.10181395
발행일
2023
유형
Proceedings Paper
저널명
IEEE International Symposium on Circuits and Systems proceedings