A 10. Gbps CMOS oversampling Data Recovery Circuit with a Fine Delay Genetation Method

초록

An 1Gbps data recovery circuit composed of an analog delay locked loop and a digital decision logic using the digital oversampling technique is described. The delay locked loop is locked to multiple clock periods to make timing resolution less than the gate delay of the delay chain. The digital logic that decides the received data is made with the assumption that there is no frequency deviation that hurts the center of acquired data. The correct functioning was verified through the simulation with 0.6um CMOS technology. The chip will be fabricated soon.