All digital DLL with three phase tuning stages

초록

This paper describes an all-digital DLL(Delay Locked Loop) circuit with a high phase resolution. The proposed architecture is based on three-stage phase tuning blocks for coarse, fine and ultra fine phase control. Each block has a phase detector, a phase selection block and a delay line, respectively. It was simulated in a 0.35um CMOS technology under 3.3V power supply using HSPICE simulator. The simulation result shows the phase resolution can be reduced to 10ps with the operating range of 250MHz to 800MHz.