시간디지털신호변환기 설계

초록

This paper describes a time to digital converter (TDC) that measures the time interval between two signals and converts to digital signals. The proposed TDC circuit has achieved a high resolution (25ps) by using a high-speed digital sampler. This circuit is designed under 3.3v supply voltage and simulated 0.35um CMOS process. The power dissipation is 177mW in simulation.