A Design and Implementation of MIPI A-PHY RTS Layer

초록

This paper implements and verifies the A-PHY and RTS layers, which are the newly proposed SerDes standards. A-PHY and RTS layers were verified using Xilinx KC705 FPGA board and Loopback module. As a result of synthesis in FPGA, it was confirmed that 3,924 LUTs, 2,019 registers, and 132 block memories were used, and the maximum operating speed was 200 MHz.

키워드