A DLL Circuit Design with Precise Delay Coordination Method

초록

This paper descrives a novel DLL circuit design with precise delay coordination method. This design consists of a main DLL and second DLL from each tap of maun DLL. The main loop generates a fixed phase step which is the function of the delay cell in the main DLL. The controllable delays in the second loop are connected to each delay tap of the main DLL and the delay is different from the delay value in the main loop. This delay difference palys role as a resolution we can control on the phase of the retimed clock. Theoretically the difference can be made very small but th resolution available in real applications will be limited by the inherent jitter in the system. A fine phase adjustment of less than 10ps can be achieved when 250MHz clocking condition.