Atomic Layer Deposition Techniques for Next-Generation Thin Film CMOS Channel Layers

초록

The atomic layer deposition (ALD) process has been used for the core technology of the latest DRAM, NAND, and Logic devices. These devices exploit the advantages of ALD processes such as superior step coverage, in-wafer uniformity, and thickness controllability. The demand for ALD processes is still highly increasing since lateral shrinking & vertical stacking trends of the latest devices. However, ALD processes that are being practically applied in the current semiconductor industry are mostly limited to dielectric thin films and electrode applications. To implement VCAT-based DRAM and monolithic 3-D devices (M3D), high-performance semiconducting thin film for transistors also need to be developed via ALD. The absence of suitable p-type and n-type semiconducting thin films deposited by ALD processes has been a major challenge that the semiconductor industry faces. Here, we demonstrated a high-performance thin-film CMOS system by adopting atomic layer deposited n-type and p-type semiconducting materials. The process temperature for fabricating CMOS devices was kept below 300°C, eliminating the thermal budget issue, which is the biggest hurdle in M3D fabrication. These notable results were achieved through phase engineering enabled by the novel precursor and effective surface/interface control. This development of complementary n-type and p-type semiconducting thin films using the ALD process is expected to pave the way for the vertical stacking of thin-film CMOS transistors and next-generation memory applications.