A 5-Gb/s Continuous-time Adaptive Equalizer and CDR using 0.18um CMOS

초록

In this paper, a 5-Gb/s receiver with adaptive equalizer and clock and data recovery(CDR) for serial link interface is proposed. In order to operate adaptively at 5-Gb/s data rate, LMS algorithm uses two internal signals from slicers which does not have an effect on gain boosting performance. In addition, this scheme enables it to operate without passive filter since two internal signals of slicers has a similar DC magnitude. The proposed adaptive equalizer in this receiver can compensate up to 20-dB and operate in various environments, which are 15-m shield twisted pair(STP) cable for DisplayPort and flame retardant 4(FR-4) traces up to 60-inch adaptively. This work is implemented 0.18-μm 1-poly 4-metal CMOS technology. Power dissipation of the equalizer is only 6-mW and it occupies 200μm x 350μm. Total power dissipation of the combined CDR is 164- mW(including output buffers) and operating range is available up to 5-Gb/s.