미세정밀 타이밍 발생회로 설계

초록

This paper describes the architecture and performance of a new high resolution timing generator used as a building block for time-to-digital converter(TDC), clock and data recovery(CDR) and time of flight(TOF). The High resolution timing generator is implemented as only single delay line of DLL(delay-locked-loop). The proposed circuit was designed using hynix 0.35um CMOS technology. Simulation show that the resolution is 25ps consuming 480mw under 3.3v power supply.