Optimized Instruction Set Architecture for Programmable Memory Test Pattern Generation

초록

Continuous progress in memory semiconductor manufacturing technology has significantly increased capacities, densities, and operating frequencies. However, these developments have also increased the probability of memory defects, consequently diminishing yield rates. To overcome this issue, various memory test pattern algorithms have been devised to identify the type of memory defect, primarily categorized into linear and nonlinear patterns. This paper presents an instruction-based approach for efficiently generating diverse nonlinear patterns. The proposed instruction set architecture (ISA) provides flexibility in generating both linear and intricate nonlinear patterns, while also ensuring a compact memory test setup cycle, regardless of the memory cell size. © 2024 IEEE.

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