계면 엔지니어링을 통한 탑게이트 박막 트랜지스터의 성능 향상 전략

초록

The development of high-performance p-type oxide thin film transistors (TFTs) is essential for realizing monolithic 3D (M3D) integration of CMOS, a key technology for the future semiconductor industry. However, most research on p-type oxide thin film transistors has focused on bottom gate structures, limiting circuit design diversity. The development of top-gate TFTs not only facilitates circuit design, but also permits the selection of an optimal substrate for ALD channel growth. The p-type SnO, which exhibits high hole mobility induced by its distinctive VBM structure, has the greatest potential for the commercialization. However, due to its metastable nature, it is susceptible to be oxidized into n-SnO2. To prevent the degradation of p-SnO in the oxidizing atmosphere used in the implementation of the top gate TFT, a thin Al₂O₃ interlayer was introduced. This results in enhanced electrical characteristics such as μFE, Ion/Ioff ratio, S.S, and hysteresis. We believe that this research will move up the realization of M3D CMOS in the industry. This research was supported by Korea Institute for Advancement of Technology(KIAT) grant funded by the Korea Government(MOTIE) (RS-2024-00409639, HRD Program for Industrial Innovation)