A 1.0 Gbps CMOS Clock and Data Recovery Circuit with Two-XOR Phase-Frequency Detector

초록

This paper describes a 1.0Gbps Clock and Data Recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector(PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The phase frequency capture range of PFD is decided by VCO operating range which is 380MHz - 720MHz. The circuit operates on 800Mbps to 1.2Gbps data rate under 2.5V supply using 0.25m-CMOS HSPICE simulation. The circuit is being under fabrication (Expected fab. out Nov.20. 2000). The measured results can be presented during the conference session.