A Low Jitter Burst-Mode Clock and Data Recovery Circuit with Two Symmetric VCO's

초록

This paper presents a burst-mode clock and data recovery (CDR) circuit based on two symmetric quadrature phase VCO’s. Compared with the conventional structure with a T/2 delay cell based approach, the proposed structure shows the better re timing margin without any delay unit for the timing control. The proposed circuit is designed and simulated in 350nm CMOS process. The simulation of the proposed CDR showed the data recovery at 1.6 Gb/s with 27-1 pattern with peak-to-peak jitter of 5.5ps.