2.5Gb/s Data Recovery Circuit with transition/Non-Transition Tracking Algorithm

초록

This paper describes a CMOS clock/data recovery circuitry using a 4X oversampling technique. Digital oversampling is done using delay-locked loop (DLL) arrays. The delay-locked loop arrays generate a very fine resolution less than the gate delay of the delay chain. The transition and non-transition tracking algorithm from 4x oversampling was implemented for a robust data recovery. The chip has been fabricated with 0.25um CMOS technology and measured results are presented