기준클럭이 없는 클럭 데이터 복원회로

초록

We described a clock and data recovery circuit with a half rate 4X oversampling PD and FD without a reference clock. The CDR circuit with PD and FD technique of 4x-oversamping can find the synchronization between input data and clock by performing digital logic operations and recover the consecutive data without an additional circuit or insertion of predefined signals. Since the circuit utilizes the digital logic for PD and FD function, it has better portability to different processes. Simulated result shows that the circuit is capable of recovering clock and data at rates of 3.125Gbps with 0.18 um CMOS technology