A CMOS mixed-Mode Phase tuning Delay Locked Loop Circuit

초록

Delay-Locked Loops(DLL's) and phase-locked loops(PLL's) are routinely employed in high-speed phase alignment circuits such as microprocessor and synchronous DRAM. Especially, due to the better jitter performance, simpler design and unconditional stability, DLL is a satisfactory substitute for VCO(Voltage Controlled Oscillator)-based PLL's in applications where no clock synthesis is required. The important drawbacks of the conventional DLL are their limited phase capture range by the absolute delay of the delay buffer. This report shows the new algorithm and architecture to achieve unlimited phase(360 degree) controllability. The DLL circuit has been designed and was fabricated using 0.65 CMOS technology. The power dissipation is about 200mW with 3.3 volt power supply and the operating frequency is between 400MHz and 500MHz. The minimum phase resolution is 10ps at 500MHz clock.