인코딩 테이블 축소에 의한 8B/10B 인코더의 설계

초록

This paper presents a design of 8B/10B encoder by coding table reduction. The existing encoding table IBM suggested(1983) requires many logic functions. But this encoder is capable of reducing the number of gates by using simple encoding table. Synthesis and simulation are tested by Xilinx’s FPGA(virtex2v1000-5fg256) & synplify pro.