Design and Analysis of Referenceless Dynamic Comparator for PAM-4 Receiver

초록

In pulse amplitude modulation 4-level (PAM-4) receiver design, the variation of the effective least significant bit (LSB) threshold voltage degrades the margin of LSB decision and worsens the bit error rate (BER). This paper proposes a dynamic comparator to solve the problem. The proposed dynamic comparator features low variability in effective LSB threshold voltage due to its common-mode-rejection capability. The proposed dynamic comparator has been designed and simulated at post-layout level in a 45 nm CMOS with 1.1 V supply voltage. The effective LSB threshold voltage variations of the conventional and proposed dynamic comparators are quantitatively analyzed and compared by simulation results.

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