A Self-Recovery Scheme for Fault-Tolerant and Side-Channel Resistant Systolic Arrays

초록

Deep Neural Network (DNN) accelerators are being actively developed with customized architectures for diverse applications. As they are increasingly adopted in security-sensitive and mission-critical systems, security and reliability have become critical requirements. However, satisfying both remains challenging. This paper presents a self-recoverable hardware architecture that achieves fault tolerance and side-channel resistance through symmetric dual-rail precharge logic (DPL). The proposed design maintains computational integrity under various fault scenarios while leveraging secure signal balancing inherent to dual-path execution. It enhances both reliability and security without compromising performance, incurring only a 0.20% increase in power consumption and a 0.89% increase in register usage, making it suitable for deployment in safety-critical and adversarial environments. © 2025 IEEE.

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