A Low-Power Counter-based Digital CDR

Citations

WEB OF SCIENCE

0
Citations

SCOPUS

0

초록

This paper presents a counter-based digital CDR. For frequency acquisition, frequency direction is determined by comparing the number of edges of input data and recovered data. And for fine frequency acquisition, FLL gain is reduced by counting the number of times as the direction signal changes. The proposed digital CDR is designed and simulated in a 28nm CMOS technology and consumes 6.5mW in 1V supply voltage with 10Gb/s input data.

키워드

All Digital Clock and Data Recovery (ADCDR)Frequency AcquisitionCounter-Based Frequency Detector(FD)Digitally Controlled Oscillator(DCO)
제목
A Low-Power Counter-based Digital CDR
저자
Kim, Hyun-InKang, Jin-Ku
DOI
10.1109/ISOCC56007.2022.10031478
발행일
2022
유형
Proceedings Paper
저널명
2022 19TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)
페이지
143 ~ 144