FPGA-Based Integer-Only Hardware Accelerator for YOLOv3-Tiny Model

초록

YOLO-based networks are frequently employed in object detection tasks due to their outstanding performance. In this work, we integrate the YOLOv3-tiny network with depthwise convolution, which excels at capturing spatial features, thereby maintaining high accuracy with a reduced parameter count. We also design an FPGA-based CNN accelerator using High-Level Synthesis (HLS) that supports line buffer and plane buffer computation schemes. Trained on the Pascal VOC dataset, the proposed network's 8-bit integer model achieved a mAP@0.5 of 65.7%, while using 74% fewer parameters than the original YOLOv3-tiny network. The accelerator is implemented on Xilinx ZC706 board, utilizing 345 BRAM18k blocks, 306 DSP slices, 25.5k FFs and 17.9k LUTs. © 2025 IEEE.

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