Scalable Multi-Site Test Architecture for Chiplet-Based Systems on ATE Platforms

초록

As chiplet technologies such as 2.5D/3D rapidly advance, chiplet testing approaches are becoming increasingly challenging. Specifically, stacking multiple chips or high bandwidth memory (HBM) in a single package increases the I/O pin count, leading to longer test times and multi-site test performance degradation due to increased test complexity and resource constraints. In turn, this results in higher testing costs as additional time and equipment are required to maintain test efficiency. In this paper, we propose a novel test interface integrating digital and analog compression modules to achieve high parallelism and precise fault detection. The proposed architecture incorporates a device under test (DUT) off masking sequence and a fault detection scheme, which enhances production efficiency while optimizing limited test resources by reusing analog test instruments that were not previously used in digital functional testing. This approach reduces overall test resource requirements and supports cost-effective parallel testing without additional equipment. Experimental results include an analysis of the architecture's operational reliability under process variations and demonstrate a reduction in test resources and an average 82.2% decrease in test data volume on the ISCAS'89 and OpenCores benchmarks compared to prior work.

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