2x오버샘플링 클럭/데이터 복원회로

초록

A CMOS clock and data recovery (CDR) circuit with 2x oversampling for multi-gigabit data rates is described. It uses multiphase clocks and parallel sampling techniques to reduce the speed requirements. The circuit can generate 1:8 demultiplexed outputs or 1:1 serial output. The circuit adopts 2x oversampling technique and phase picking data recovery. Since the circuit oversamples twice per bit period (2x), the chip area and power consumption can be reduced compared to 3x or 4x oversampling CDR. The proposed circuit was designed using TSMC 0.35um CMOS Technology. Simulation results show that the circuit is capable of recovering clock and data at a speed of 2.5 Gbps and consuming 230mW under 3.3V power supply.