A 20-Gb/s PAM-4 Receiver with Dual-mode Threshold Voltage Adaptation using a Time-based LSB Decoder

초록

This paper presents a pulse amplitude modulation-4 (PAM-4) receiver with dual-mode threshold voltage applied to a time-based LSB decoder. The proposed receiver can select the threshold voltage that improves the robustness to sampler voltage variations. It also presents a random data-based threshold voltage adaptation using a single error sampler. Compared to the conventional PAM-4 threshold voltage adaptation that finds four data levels, this method finds only two levels, which reduces the overall power consumption, hardware complexity and adaptation time. The 20-Gb/s PAM-4 serial link was designed in a 65 nm CMOS Technology and analyzed with XMODEL and Cadence Design System's Spectre. A channel with 15.36 dB loss at Nyquist frequency was compensated through a two-stage continuous-time linear equalizer (CTLE), a variable gain amplifier (VGA). The simulation results demonstrate proper convergence of threshold voltage and reduce the threshold adaptation time compared to the conventional. The power consumption of the receiver is only 29 mW. The power efficiency of the receiver is 1.45 pJ/bit.

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