8B/10B Encoder Design By Encoding Table Reduction

초록

It is compare the encoder for reduction of encoding table & modification of disparity block and the encoder of IBM proposed it through synthesizing. Table 6 is simulation result through xilinx Virtex2 chip about logic gate and maximum frequency of each encoder. As Design and analysis consequences, number of logic gates decrease 114 to 95 (about 17%) and number of DFF decrease 17 to 12 (about 30%) Also, it is affirmed that speed increases about 14% through simulation result on using Xilinx’s Virtex2v 1000-5fg256.