A Self -Timed Wave Pipelined Adder Using Data Align Method

초록

In this paper, a 32bit wave pipelined adder circuitry using the static CMOS plus data-aligning logic is presented. The self-timed wave-pipelining algorithm was implemented in the circuit design. The data aligning logic in the algorithm is consisted of the double edge triggered flip-flop detecting the slowest arrived signal, the aligning signal generator, and latches. Using the algorithm, the delay variation of signals at the output of the 32-bit adder could be controlled under 130ps rather than 766ps in a conventional adder. The circuit operates at 800M/bps data rate using 0.25m CMOS technology with 2.5V supply voltage.