20Gb/s Energy Efficient and Linearity Enhanced Integrated Summer Latch-based PAM-4 DFE

초록

This work presents an integrated summer latch (ISL)-based DFE with advantages in low power and enhanced linearity. The proposed architecture enhances linearity by alleviating the equalization variation arising from summing node output differences among high, middle, and low slicers. Furthermore, sharing preamplifiers across the slicers reduces hardware complexity and power consumption. A reduced tap loading scheme is applied to the PAM-4 ISL DFE, enabling low-power operation with 2-tap configuration. Improved energy efficiency with sufficient eye-opening were verified through simulations in a 45nm CMOS process with a 1.1V supply voltage.

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