A CMOS Clock and Data Recovery with Two-XOR PFD Circuit

초록

The proposed circuit is based on a single loop controlled by a Phase Frequency Detector(PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45. The PFD generates the VCO control signal by comparing two different phase clocks and input data.. The circuit operates on 800Mbps to 1.2Gbps data rate under 2.5V supply using 0.25m-CMOS HSPICE simulation. The circuit is being under fabrication. The measured results can be presented during the conference session.