A 1.25Gb/s Clock recovery circuit using half-rate 4x oversampling PD

초록

In this paper, a clock and data recovery (CDR) circuit for a serial link with a half rate 4x oversampling phase frequency detector (PFD) structure is described. The PFD is designed by 4X oversampling method. The PFD finds the data_ lead and data _lag by the logical computation to the input data and controls amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the TSMC 0.25um CMOS technology and operating voltage is 2.5V. The circuit is operating between 480Mb/s ?1.5Gb/s.