High-speed Serial Interface using PWAM Signaling Scheme

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초록

This paper presents a novel PWAM signaling scheme, which improves the high-speed data transmission capability by increasing the minimum pulse width compared to the conventional PWAM scheme. In addition, versus the existing PAM, the power efficiency of the transceiver employing a novel PWAM signaling scheme is improved by the PWM modulator based on CMOS logic. The 10-Gb/s transceiver designed for a 0.18-mu m CMOS process consumes 229 mW and has a power efficiency of 22.9 pJ/bit.

키워드

CMOSpulse amplitude modulation (PAM)pulse width modulation (PWM)serial linklow powertransceiverLINKPWM
제목
High-speed Serial Interface using PWAM Signaling Scheme
저자
Kim, Hwan-UngKang, Jin-Ku
DOI
10.1109/ISOCC56007.2022.10031330
발행일
2022
유형
Proceedings Paper
저널명
2022 19TH INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC)
페이지
255 ~ 256