SDC-aware Masking Scheme for Biased SEUs and Directional Bit-Flipping

초록

Soft errors caused by radiation-induced Single Event Upsets (SEUs) have become a critical concern in recent logic circuits, particularly in LUT-based architectures used in FPGAs. This paper proposes an SDC-aware masking scheme that incorporates both SEU directional bias and realistic input vector distributions. Our approach improves masking effectiveness by focusing on frequently occurring input combinations and applying a bias to bit-flip directions. This is expressed as a generalizable formula for N input LUTs. This equation is suitable for integration into logic synthesis and optimization flows targeting radiation-sensitive environments. Simulation results obtained from a Python-based fault injection framework for LUT-based logic circuits demonstrate the effectiveness of SDC-aware fault mitigation. By incorporating both test vector usage frequency and the directional bias constant into the masking strategy, our algorithm achieved up to a 34.2% reduction in failure rate compared to incorrect masking under asymmetric SEU conditions. © 2025 IEEE.

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