Analysis of a Data Recovery Circuit with Digital Oversampling Technique

초록

In this paper we analyzed a data recovery system using the oversampling technique. The input waveform is assumed to be non-return-zero (NRZ) binary signals. A finite Markov chain model is used to evaluate the steady-state phase jitter performance of the data recovery system in the presence of input noise. Theoretical results are able to predict the input signal-to-noise ratio (SNR) versus bit error rate (BER) of the data recovery system for various oversampling ratios. The more number of samples per single bit results in the better performance on BER at the same input SNR. To achieve BER, 8 times oversampling has about 2dB input signal penalty compared to 16 times oversampling. In an architectural choice of the oversampling data recovery circuit, the recovered clock can be updated in each data bit or in every multiple bits. Two different clock update schemes were analyzed and compared. The scheme updating clock in every data bit has about 1.5dB penalty against the multiple bits (4 bits) clock updating scheme with 16 times oversampling.