A Two-Phase Test Point Insertion Scheme for Low-Power Scan Testing

초록

As semiconductor device and process technologies advance, the increasing number of integrated IPs per chip emphasizes the need for improved test reliability. Test point insertion (TPI) is a commonly adopted and efficient solution for enhancing the test coverage; however, it often increases power consumption during test. To address this issue, this paper proposes a new Gated Shared Flip-Flop (GSFF) architecture and a two-phase test scheme. The GSFF architecture employs dynamic data gating to directly control the data path. Experimental results confirm that this approach effectively reduces dynamic power consumption while minimizing area overhead compared to conventional methods. © 2025 IEEE.

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