4X-oversampling 기법의 PFD를 이용한 1.25Gbps 클락 및 데이터 복원회로

초록

In this paper, a 1.25Gbps serial link clock and data recovery (CDR) circuit with a simple PFD structure is described. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD). The PFD is designed by 4X oversampling method. The PFD finds the data_ lead and data _lag by the logical computation to the input data and controls an amount of current that flows through the charge pump. The VCO composed of four differential buffer stages generates eight differential clocks. Proposed circuit is designed using the TSMC 0.25um CMOS technology and operating voltage is 2.5V.