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서영교 프로필 사진

서영교

SEO, YEONG KYO

공과대학

전기전자공학부

2020

2026

연도별 연구 활동 현황

전체 68건 중 1번부터 10번까지의 결과를 표시합니다.

2026

Article

AOI-Based Novel Majority Approximators for Energy-Efficient On-Chip Data Bus Inversion

Article

High-Performance and Energy-Efficient Computing-In-CAM Design for Binary Neural Network Acceleration

2025

Article

AlScN-based ferroelectric memristor for electrical synapse emulation and light-stimulated reservoir computing

Article

Multifunctional ferroelectric synaptic memristors based on HfAlOx with enhanced Pavlovian learning and physical reservoir computing systems

Article

Polarity-dependent dual-mode AlN-embedded RRAM with improved stochastic switching and synaptic modulation for neuromorphic computing

Article

Network Splitting Techniques and Their Optimization for Lightweight Ternary Neural Networks

Article

Batchnorm-Free Binarized Deep Spiking Neural Network for a Lightweight Machine Learning Model

Article

Energy-Efficient Hybrid Spin-CMOS Logic Design Based on Cascadable Spin-Torque Majority Gate

Article

Restoring-free Transposable eDRAM-based Computing-In-Memory System for SNN On-chip Unsupervised STDP Learning

Article

A Pass-Transistor Logic-Based Hybrid Approximate Full Adder Composition with Reduced Error

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서영교

자료유형

발행연도

키워드

언어

AOI-Based Novel Majority Approximators for Energy-Efficient On-Chip Data Bus Inversion

High-Performance and Energy-Efficient Computing-In-CAM Design for Binary Neural Network Acceleration

AlScN-based ferroelectric memristor for electrical synapse emulation and light-stimulated reservoir computing

Multifunctional ferroelectric synaptic memristors based on HfAlOx with enhanced Pavlovian learning and physical reservoir computing systems

Polarity-dependent dual-mode AlN-embedded RRAM with improved stochastic switching and synaptic modulation for neuromorphic computing

Network Splitting Techniques and Their Optimization for Lightweight Ternary Neural Networks

Batchnorm-Free Binarized Deep Spiking Neural Network for a Lightweight Machine Learning Model

Energy-Efficient Hybrid Spin-CMOS Logic Design Based on Cascadable Spin-Torque Majority Gate

Restoring-free Transposable eDRAM-based Computing-In-Memory System for SNN On-chip Unsupervised STDP Learning

A Pass-Transistor Logic-Based Hybrid Approximate Full Adder Composition with Reduced Error